The most recent advances in semiconductor memory storage devices have occurred in flash memory. Flash memory is nonvolatile and therefore memory states are retained without the need for supplying power to the flash memory. Flash memory devices are rapidly replacing read only memory (ROM) chips in desktop applications, and because they will retain memory states without power, flash memory devices are becoming the alternative to electrically erasable and programmable read only memories (EEPROM). The nonvolatility characteristic makes flash memory devices ideal for applications in which low power consumption is an important design criterion, such as in portable computer and data terminal systems where flash memory is replacing hard disk drives as the main random access semipermanent memory storage device.
A current problem encountered in digital microprocessor applications is that the bandwidth (operating speed) of the microprocessors far exceeds the bandwidth of the random access memory devices. This bandwidth mismatch often places the microprocessor into an unproductive wait state wherein the microprocessor spends extra cycles waiting for the operation to be performed by the memory to be completed. Static random access memory (SRAM) devices have higher bandwidths than do dynamic random access memory (DRAM) devices but SRAMs are more costly and have lower memory densities than do DRAMs. It is for these reasons that DRAMs are preferred over SRAMs where cost and space are at a premium.
In order to improve the bandwidth of DRAM memory systems and thereby reduce the bandwidth gap between the microprocessor and the main random access memory, many designs employ SRAM devices and DRAM devices together in a circuit arrangement known as a cache hierarchy in order to maximize the respective advantages of both memory technologies. In cache hierarchy architecture, a small SRAM memory device is placed between the microprocessor and a large bank of DRAM memory devices. The SRAM acts as a memory buffer between the microprocessor containing information most frequently requested by the microprocessor that the SRAM can transfer to and from the microprocessor at a faster rate than the DRAM could do directly. Multiple variations of this cache hierarchy exist with different implementations designed to improve access time to the random access memory.
In applications where an entirely solid state memory device is desired as the main random access memory to be used in place of electromechanical memory storage devices, DRAM devices are used to implement a virtual RAM disk. However, DRAM memory is volatile and requires external power in order to preserve the saved memory states. The nonvolatility of flash memory makes it an ideal replacement to DRAM memory devices because no external power is required to maintain the memory contents of flash memory. Flash memory read access times are of the same order of magnitude as DRAM read access times, however flash write and erase speeds are much slower. Therefore cache hierarchy architecture with flash memory implementations is required even more so with flash memory than with DRAM memory.
The basic memory element in flash memory designs is a complementary metal oxide semiconductor (CMOS) transistor which is a subclass of field-effect transistors (FETs). The gate voltage on the flash transistor memory cell floats with respect to ground, that is the gate voltage is electrically isolated from the rest of the transistor circuit. To save a memory state to the flash memory cell (i.e. perform a write to the memory cell), the gate of the CMOS transistor is connected to the supply voltage, the source of the transistor is grounded, and the drain of the transistor is biased to an intermediate voltage, typically one half of the supply voltage. In this configuration, the drain of the CMOS transistor is at a higher voltage than the source of the transistor, and negatively charged electrons flow from the source to the drain. Since the gate is also at a positive voltage with respect to the source, some of the electrons flowing from the source to the drain will reach a high enough energy state to tunnel through the oxide layer barrier. These so called "hot" electrons remain on the floating gate, and therefore the threshold voltage required to turn on the transistor is increased.
In order to change the saved memory state (i.e. perform an erase of the memory cell), the reverse of the aforementioned write procedure is performed. To perform an erase the gate of the CMOS transistor is negatively biased with respect to the source of the transistor; typically the source is connected to the supply voltage and the gate is grounded. Thus the electrons that accumulated on the floating gate in the write process tunnel back again through the oxide layer in a process known as Fowler-Nordheim tunneling. This flash memory write and erase process is similar to that used in erasable programmable read only memory (EPROM) design, however the main difference between the two is that the oxide layer in the flash design is thinner than in the EPROM design in order to allow for the flash erase process to be accomplished electrically whereas the EPROM erase process requires exposure of the device to ultraviolet (UV) radiation in order to give the accumulated electrons enough energy to tunnel (Fowler-Nordheim tunneling) back through the EPROM's thicker oxide layer.
Because the flash memory cell CMOS transistor has a relatively thin oxide layer in order to allow for electrical memory erases, the tunneling process will eventually wear out the oxide layer of the flash CMOS transistor. Thus the lifetime of the flash memory device is limited to a certain number of write and erase cycles which typically range from 10,000 to 1,000,000 cycles. Additionally, the wear encountered on the oxide layer of the flash memory cell CMOS transistors is not evenly distributed across the entire flash memory array. If the flash memory device is used in random access applications such as a solid-state implementation of a hard disk drive, some of the flash memory cells will undergo more write and erase cycles than other cells causing some cells to wear out more rapidly than other cells, thereby wearing out the flash memory device and ending its useful life sooner than if the write and erase cycles had been more evenly distributed among all of the transistors in the flash memory array.
Flash memory chip manufacturers are designing flash memory devices that make the slow write and erase cycles less noticeable and that additionally distribute wear more evenly across the entire memory device. In addition there exist software and hardware implementations of flash memory which intelligently manage flash memory device wear by periodically rearranging memory blocks so that information stored in relatively inactive memory blocks is relocated to relatively active memory blocks thereby freeing the inactive blocks so they may be written upon. The number of times a block of memory has been erased is also monitored by this type of system software in order to identify which memory blocks are likely to be close to wearing out. However no method exists that determines the exact number of writes that are available to the flash memory.